1. Field of the Invention
The present invention relates to a memory card with nonvolatile memories of a block erasure type on board.
2. Description of the Prior Art
FIG. 6 is a block diagram schematically showing an example of a conventional memory card mounting flash memories which are nonvolatile memories of a block erasure type.
In FIG. 6, a memory card 50 consists of an interface circuit 51, an internal control CPU 52, a buffer memory 53 for inputting/outputting of data, a flash memory control circuit 54 and a memory part 55 composed of flash memories. The internal control CPU 52 is connected to the interface circuit 51 and the buffer memory 53, and also connected to the memory part 55 via the flash memory control circuit 54. When the memory card 50 of the constitution is connected to a host system apparatus 60 formed of a data processor, the host system apparatus 60 is brought into a connected state with the internal control CPU 52 via the interface circuit 51.
In the above state, the interface circuit 51 inputs/outputs data to the host system apparatus 60. The internal control CPU 52 controls signals in the memory card 50, and the flash memory control circuit 54 controls the memory part 55 in accordance with control data such as read/write commands, address data, etc. sent from the internal control CPU 52 to the memory part 55. For example, when the number of a sector is input from the internal control CPU 52, the flash memory control circuit 54 generates address data for the memory part 55 corresponding to the input sector number and outputs the data to the memory part 55.
Each flash memory as a component of the memory part 55 is electrically erasable memory, erasing data every erasure block of several K bytes to several tens of K bytes at a time. Data cannot be overwritten on the same address in the flash memory. While the flash memory of the memory part 55 is capable of writing or reading data only every 8 bits or 16 bits, the memory part 55 is required to send/receive data every 512 bytes to the host system apparatus 60, and therefore the buffer memory 53 is used as a cache memory between the internal control CPU 52 and memory part 55.
In general, there are several to several tens of flash memories mounted as an IC memory in the memory part 55 and, each flash memory has a plurality of erasure blocks. FIG. 7 is a diagram of an example of a memory map in the flash memories constituting the memory part 55 of FIG. 6. In FIG. 7, addresses of two flash memories 70, 71 each having a data width of 8 bits and erasure blocks of 64 KB each are connected parallel to each other, thereby attaining the data width of 16 bits. Respective 8 erasure blocks A-H are made to correspond each other in the flash memories 70, 71.
In the constitution of FIG. 7, even a single defective erasure block in the flash memory 70 or 71 generates an area not accessible from the host system apparatus in the memory space, whereby not a single byte of the partially defective flash memory is useful. The flash memories 70, 71 should accordingly be completely non-defective, and defective flash memories have been conventionally discarded, which leads to an increase of costs of the memory card.
Although it has been arranged in certain memory cards to use perfect erasure blocks alone with prohibiting the use of defective erasure blocks, when a plurality of flash memories are used in the manner as illustrated in FIG. 7 and if an erasure block A of the flash memory 70 is defective as well as an erasure block B of the flash memory 71, both erasures blocks A and B in each of the flash memories 70 and 71 become unusable. In other words, the erasure block of one flash memory corresponding to the defective erasure block of the other flash memory becomes unusable although it is not defective. The memories have been thus used inefficiently in the conventional memory card.